As an example of signal processing apparatus, sigma-delta modulator is known. The configuration of a conventional and typical fourth order sigma-delta modulator is shown in FIG. 4.
In FIG. 4, a digital signal is inputted into an input terminal 57. For the sake of convenience, we assume that the input digital signal is a 20-bit signal. In this case, the input terminal 57 consists of 20 terminals. 58, 63, 68, and 73 are 20-bit input and 20-bit output adders. 60, 65, 70, and 75 are 20-bit input and 20-bit output delay elements, and they output their input values delayed by one clock.
The adder 58 and the delay element 60 constitute a 20-bit input and 20-bit output accumulator. That is to say, the adder 58 adds the input digital signal 57 to the output signal of the delay element 60, which is the output signal of the adder 58 delayed by one clock. The addition result is outputted to a line 59. If there is an overflow as a result of the addition, a 1-bit overflow signal 62 will be outputted to an overflow line.
A block consisting of the adder 63 and the delay element 65 also constitutes an accumulator, and its input is the output signal of the adder 58, i.e. the output signal of the accumulator consisting of the adder 58 and the delay element 60. Likewise, a pair of the adder 68 and the delay element 70, and a pair of the adder 73 and the delay element 75 also constitute a respective accumulator, therefore the configuration is such that four accumulators are connected in cascade.
67, 72, and 77 are overflow signals of the adders 63, 68, and 73, respectively.
A concrete configuration example of the constituent element 79 is shown in FIG. 5. 35, 37, 39, 41, 43, and 45 are delay elements, which output their input values delayed by one clock. 36, 38, 40, 42, 44, and 46 are subtractors, which subtract the input values affected by the respective delay element from the input values unaffected by the respective delay element, and output the result of the subtraction. The inputs of 48, an adder with four inputs, are the overflow signal 62, the outputs of the subtractors 36, 40, and 46.
With this configuration, the constituent element 79 has the functions of receiving the overflow signals 62, 67, 72, and 77 outputted by the accumulators 58, 63, 68, and 73, summing the overflow signal 62, the result of first order differentiation of the overflow signal 67, the result of second order differentiation of the overflow signal 72, and the result of third order differentiation of the overflow signal 77, and then outputting the summing result from the terminal 80.
A whole block consisting of the said four accumulators and the constituent element 79 constitutes a fourth order sigma-delta modulator. Its input terminal is 57, and output terminal is 80. Likewise, an nth order sigma-delta modulator consists of n accumulators, and an element that receives and processes the overflow signals of each accumulator.
In this conventional technology, for example, since an nth order sigma-delta modulator corresponding to an input signal with 20-bit dynamic range requires n 20-bit accumulators and n 20-bit delay elements, the circuit scale will be big. This not only entails some disadvantages such as increases in chip area and consumption current, but also increases the noise leaking to the power supply line and the ground line while operating.
Such sigma-delta modulator is used widely as a constituent element of fractional frequency divider. The related technology is disclosed in U.S. Pat. Nos. 4,609,881, 4,758,802 and 4,965,531.
The general configuration of a fractional N-PLL synthesizer is shown in FIG. 6. In FIG. 6, the output of a VCO 84 is split into two signals. One becomes a final output 88 of the PLL synthesizer, and the other is inputted into an integer divider 86. The output divided by the integer divider 86 is inputted into the phase comparator (PD hereafter) 81. As the other input, a reference signal 87 is inputted into PD 81, and the phase difference between the reference signal 87 and the output signal of the integer divider 86 is outputted to a charge pump(CP hereafter) 82. The CP 82 converts the phase difference information it receives into current or voltage, which is fed back to the VCO 84 after passing through a loop filter (L.F. hereafter) 83. By the function of this feedback, the frequency of the signal that VCO 84 outputs is locked to a frequency of the reference signal 87 multiplied by a frequency division ratio (termed “division ratio” hereinafter).
In the configuration of FIG. 6, by having the division ratio control device 85 change the frequency division ratio of the integer divider 86 over time, non-integer division ratio is realized as a time average value. Sigma-delta modulator is used as such a division ratio control device. When a sigma-delta modulator is used as a constituent element of a fractional N-PLL synthesizer, its big circuit scale results in disadvantages such as increases in chip area and consumption current, and an inferior C/N ratio due to the noise leaking to the power supply line and the ground line while operating.
As described above, since an nth order sigma-delta modulator requires n adders and n delay elements, it has the shortcoming that the circuit scale is big. With a fractional N-PLL synthesizer utilizing a sigma-delta modulator, the big circuit scale of the sigma-delta modulator results in disadvantages such as increases in chip area and consumption current, and an inferior C/N ratio due to the noise leaking to the power supply line and the ground line during the operation of the sigma-delta modulator.
The present invention aims at solving the problems described above, and it is an object thereof to provide a signal processing apparatus with a small circuit scale.
Another object of the present invention is to provide a non-integer divider equipped with the signal processing apparatus described above.
A further object of the present invention is to provide a fractional N-PLL synthesizer equipped with the non-integer divider described above.